1. Field of the Invention
The present invention relates to a data reading circuit for a semiconductor memory device.
2. Description of the Related Art
The integration and operation speed of recent semiconductor memory devices has become higher and faster, respectively, and a great effort has been made to reduce their supply voltage in order to ensure lower power consumption. A data reading circuit for use in such a semiconductor memory device should have a faster reading speed without failing to reduce the supply voltage.
FIG. 1 illustrates an SRAM of a pulse word type, which selects a word line in synchronism with a clock signal. A pulse generator 1 generates an internal clock signal CLK based on an input external clock signal CK. A column decoder 2 sends a column select signal to a column selector 3 based on a column address signal ADc which is input externally.
A row decoder 4 receives the clock signal CLK and a row address signal ADr. When the clock signal CLK goes to an H (High) level, for example, the row decoder 4 selects one of multiple word lines WL based on the row address signal ADr.
Memory cells C are connected to each of the word lines WL and between individual pairs of bit lines BL and /BL. Based on the word line WL selected, cell information is read from the memory cells C, connected to the selected word line WL, to the individual pairs of bit lines BL and /BL.
The column selector 3 selects one pair from plural pairs of bit lines BL and /BL based on the column select signal and transfers the cell information read on this bit line pair BL and /BL to data buses DB and /DB. A main sense amplifier 5 amplifies the cell information output onto the data buses DB and /DB and outputs the amplified information as data OUT and /OUT.
The aforementioned clock signal CLK is input to a precharge circuit 6, which is provided between each pair of bit lines BL and /BL. When no word line WL is selected, i.e., when the clock signal CLK has an L (Low) level, the precharge circuit 6 is enabled and the potential of each bit line pair is reset to V.sub.cc /2, for example, where V.sub.cc is a high-potential voltage supply.
To increase the memory capacity of this SRAM, the memory cell array becomes miniaturized more and more. The miniaturization of the memory cells C decreases the load drive performance of the memory cells C. The micronization of the memory cell array has resulted in a greater parasitic capacitance and greater parasitic resistance of the bit lines BL and /BL.
To drive the bit lines BL and /BL with large parasitic loads by the memory cells C having a smaller load drive performance and to improve the reading speed, the amplitude of cell information to be read on the bit lines BL and /BL may be suppressed, and a differential amplifier having a high input sensitivity may be used for the main sense amplifier 5.
FIG. 2 shows a main sense amplifier 5a for use in an SRAM, the bit lines BL and /BL of which are driven by cell information with a small amplitude. The bit lines BL and /BL are connected to the high-potential voltage supply V.sub.cc via respective load resistors R1. The resistance of each load resistor R1 is set so as to suppress the amplitude of the bit lines BL and /BL to approximately 100 mV to 50 mV by voltage-dividing the supply voltage V.sub.cc by this load resistance R1 and the ON resistance of the transistor that constitutes each memory cell C.
In the main sense amplifier 5a, NPN transistors Tr1 and Tr2 have their bases respectively connected to the data buses DB and /DB and collectors connected via respective resistors R2 to the voltage supply V.sub.cc.
The emitters of the transistors Tr1 and Tr2 are connected to a low-potential voltage supply V.sub.ss via an N channel MOS transistor Tr3, the gate of which is supplied with an enable signal LE via an inverter circuit 6a. Read data OUT and /OUT are output from the collectors of the transistors Tr1 and Tr2.
If the main sense amplifier 5a is constituted by a differential amplifier comprised of bipolar transistors as in this case, when the enable signal LE becomes an L level, the transistor Tr3 is turned on to enable the main sense amplifier 5a. Consequently, the minute potential difference between the data buses DB and /DB originated from the read cell information is amplified by the operation of the transistors Tr1 and Tr2 and is output as the read data OUT and /OUT.
As the supply voltage V.sub.cc gets lower, the input sensitivity of this main sense amplifier 5a falls. The resistance of the load resistor R1 for setting the amplitude of the bit lines should be set in accordance with a change in the supply voltage V.sub.cc or changes in the parasitic capacitance and parasitic resistance of the bit lines. Further, it is very troublesome and practically difficult to set the resistance of the load resistor R1 so that the amplitude of the bit lines BL and /BL is optimized in accordance with the input sensitivity of the main sense amplifier 5a.
In view of the above, one structure has been proposed that allows the memory cells C to effect the full amplitude operation of the bit lines BL and /BL according to the potential difference between the high-potential voltage supply V.sub.cc and the low-potential voltage supply V.sub.ss based on the operation of reading cell information from the memory cells C.
FIG. 3 shows the specific structure of a main sense amplifier 5b, which is used in this type of bit line full amplitude system. In this main sense amplifier 5b, a differential amplifier is comprised of MOS transistors. P channel MOS transistors Tr4 and Tr5 have sources connected to the high-potential voltage supply V.sub.cc and gates connected together to the drain of the transistor Tr4 and the drain of an N channel MOS transistor Tr6.
The transistor Tr6 has a gate connected to the data bus DB and a source connected to the drain of an N channel MOS transistor Tr8. The transistor Tr5 has a drain connected to the drain of an N channel MOS transistor Tr7, the gate of which is connected to the data bus /DB. The source of the transistor Tr7 is connected to the drain of the transistor Tr8.
The enable signal LE is input via an inverter circuit 6b to the gate of the transistor Tr8, the source of which is connected to the low-potential voltage supply V.sub.ss. An output signal OUT is output from the drains of the transistors Tr5 and Tr7, and an output signal /OUT is output from the drains of the transistors Tr4 and Tr6.
While the potentials of the bit lines BL and /BL are increased to the potential difference between the high-potential voltage supply V.sub.cc and the low-potential voltage supply V.sub.ss, the main sense amplifier 5b operates and outputs the output signals OUT and /OUT with full amplitudes when the amplitudes of the potentials of the bit lines BL and /BL become equal to or higher than a predetermined value. While the main sense amplifier 5b operates slower than the main sense amplifier 5a shown in FIG. 2, it can secure the operational margin with respect to the low supply voltage more easily.
The data reading operation for an SRAM of such a bit line full amplitude system will now be discussed with reference to FIG. 4. Assume that the individual bit lines BL and /BL are precharged to V.sub.cc /2, and specific bit lines BL and /BL are selected by the column selector 3 based on the column select signal. When the clock signal CLK goes high in this situation, a specific word line WL selected by the row decoder 4 based on the row address signal ADr goes high.
Consequently, cell information is read to the bit lines BL and /BL from the memory cell C selected by that word line WL producing a potential difference between the bit lines BL and /BL. This potential difference gradually increases.
When the enable signal LE falls to an L level to enable the main sense amplifier 5b, the main sense amplifier 5b amplifies the potential difference between the bit lines BL and /BL and inverts the read data OUT and /OUT with the full amplitudes, for example.
When the clock signal CLK falls to an L level, the selected word line WL goes low from the H level and the potentials of the bit lines BL and /BL are reset to V.sub.cc /2 by the precharge circuit 6.
In the SRAM of the bit line full amplitude system, the micronization of the memory cell array reduces the load drive performance of each memory cell C and increases the parasitic capacitances and parasitic resistances of the bit lines BL and /BL. This elongates the time from the rising of the word line WL to the H level to the point where the amplitudes of the bit lines BL and /BL become high enough to satisfy the input sensitivity of the main sense amplifier 5b based on the operation of the memory cells C. Therefore, the data reading speed cannot be increased sufficiently, disadvantageously.